The present invention relates, in general, to the field of powergating in integrated circuits, such as integrated circuit memories. More particularly, the present invention relates to a powergating method and apparatus in which the internal switched power supply voltage rails are fixed at a mid-point voltage during the standby mode of operation.
Various approaches to powergating have been used in the past wherein the internal or powergated internal power supply voltage rails are allowed to float during the low leakage standby mode. Since the floating voltage is not controlled, the internal power supply voltages can traverse the entire voltage range from the VCC power supply to the VSS power supply. Alternatively, other prior art approaches force the internal rail to the opposite power supply voltage during the standby mode. For example the internal VCC rail may be forced to a voltage at or near VSS, whereas the internal VSS rail may be forced to a voltage at or near VCC.
Both of these two powergating approaches can be present reliability problems due to excessive voltage across the gate oxides of the powergating switching transistors. For thin oxide devices, this excess voltage could cause breakdown and other reliability problems. Alternatively, these two powergating approaches could create manufacturability and cost concerns by requiring a thicker gate oxide where a thinner gate oxide would be preferred.
A typical prior art powergating circuit is shown in FIG. 1. Powergating circuit 10 includes a P-channel transistor M1 having a source coupled to the VCC power supply, a gate for receiving the PPG control signal for switching between the active and standby modes, and a drain for providing the switched PGVCC internal power supply voltage. Powergating circuit 10 also includes an N-channel transistor M2 having a source coupled to the VSS power supply or ground, a gate for receiving the NPG control signal for switching between the active and standby modes, and a drain for providing the switched PGVSS internal power supply voltage. A power-controlled circuit 12 has its power supply terminals coupled to the internal power supplies provided by the drains of transistors M1 and M2.
The reliability problem referred to above could be exacerbated if the PPG and NPG control signals are at boosted voltage levels as taught in co-pending U.S. patent application Ser. No. 10/325,524, entitled “Powergate Control Using Boosted and Negative Voltages”, filed on Dec. 19, 2002, which is hereby incorporated by reference. Referring to FIG. 2, during standby, either PGVCC goes to or near VSS or PGVSS goes to or near VCC. The PGVCC voltage is shown to undesirably extend below a mid-point voltage 14 in FIG. 2. Similarly, the PGVSS voltage is shown to undesirably extend above a mid-point voltage 14 in FIG. 2. The PPG control signal may go to a voltage above VCC and the NPG control signal may go to a voltage below ground or VSS. In this case the voltage across the gate oxides of transistors M1 or M2 (specifically the gate-to-drain voltage) could become too large and cause breakdown.
What is desired is a simple powergating circuit for use in an integrated circuit that addresses the reliability problems posed by prior art powergating circuits due to excess voltage dropped across the powergating switching transistors.